Implementation of Reversible Logic Gates for 8-Bit Multiplier

Abstract

In this paper we proposed an 8 bit fast multiplier using reversible logic gates. This multiplier can produce very less delay as compared to general multiplier in practically. Speed of execution is an important parameter while designing an digital signal processors hence by using this fast multiplier the performance of DSP processor is improved. Reversible logic gates can be widely used in further computing technologies because they dissipate zero heat under ideal conditions, zero power dissipation under ideal conditions. Multipliers are vital components of any processor. The performance of a microcontroller and digital signal processors is evaluated on the basis of number of multiplications performed in unit time. The main aim of this project is to design a multiplier based on Booths algorithm by using reversible logic gates.

Keywords: Reversible logic gates, Booths algorithm.