Leakage Resilient Adder using Dual Rail, Single Clock Adiabatic Logic against DPA Attacks

Abstract

The Innovation in the technology of electronic gadgets is because of the shirking of the technology nodes in the field of VLSI Chip design. The security of these gadgets is taken care by many cryptographic systems and the major threat to this hardware is side channel Attacks. There are  various  forms of attacked defined such as Simple Power Analysis(SPA), Differential Power Analysis(DPA), Mutual Information Attack(MIA), Correlation  Power Analysis(CPA) etc., out of all the DPA  attack  plays a vital role. In cryptographic systems the Security plays an important role in the area of E-commerce applications and military applications. The processing power of the VLSI chip is the major elements that causes SPA and DPA attacks.  The software security of data is acquired by the latest cryptographic algorithm such as Advance Encryption Standard (AES) but the crypt-analysis is a treat to this security.   In  this  paper a Dual  Rail, Single Clock Positive Feedback Adiabatic Logic (SCPFAL) is introduced which reduced the energy dissipation and also  producing  uniform power  and  current  traces  and  is  verified  by implementing and comparing the basic gates  and  a  1-bit  and  4-bit  Dual  Rail  SCPFAL Adder with existing techniques. The efficiency of the 4-bit Adder is verified by comparing with  other  DPA  resistant  logic styles such  as  SABL,  WDDL,  DDPL,  Normalized DDPL  and  PFSAL.  Security metrics are used for defining the attack immunity is Coefficient of Deviation (CoD). The implementation of logic and the results are verified by the 45nm technology of Cadence Virtuoso and the competency is defined in terms of Power, energy, and CoD with respect the temperature variation as well.

Keywords: Side Channel Attack, Adiabatic Logic, Differential Power Analysis attack.