A Simplified Approach for the betterment of Linearity in a 10-bits Segmented Current Steering DAC

Abstract

An analog signal is a route and base of any type of communication. Our universe is full up of analog signals which later converted to digital form for many uses [1]. To make a successful communication process between DSP chips and power amplifiers, the role of digital to analog converter (DAC) is very important and it acts like a path between them. Data converters are always playing like a channel for the communication process as the communication system is based on the bandwidth value [2]. This paper describes the construction, design, principle of operation, and the needs of a specially designed current steering DAC (Segmented format) having resolution of 10-bit and can produce a better linear output than the currently existed DAC. The main concept behind its construction is to maintain the balance between chip area consumption and accuracy with the help of a suitable current source. This sketched-form of DAC can be done with the help of a popular and demanded software Cadence Virtuoso (Version: - IC-615) which the product of National Semiconductor, USA using 180 nm technology. The 10-bit DAC is divided into 2 parts, each having 5-bits. The 5 MSB bits can be implemented by using a unary DAC and the rest 5 LSB bits can be implemented by using a binary DAC [6]. The former DAC is used to increase the linearity in the output and the latter is used for reduction in the implementation area of the chips which can be achieved with the compromising in linearity. But with some special care, and manipulation in design, proper linear output can be attained even after decreasing the chip designing area [18].