Development of Verification IP for AMBA AXI 5.0 Protocol

Abstract

With the recent development in IP based System on Chip (SoC) design, SoC design has become more complex with new IPs or modules used to integrate and chips are designed with goal of  less time to market. So the interconnection of IPs on Soc is made with standardized signal bus architecture, standardized bus architecture has become major integration in Soc design which helps in minimize design time. In a chip design life cycle verification takes 70% -80% of time to market. It has become very complicated to verify SoC design  with conventional methods of verification as they lack flexibility in environment for verification. Verification Intellectual Properties do come in handy while verifying the standard protocol. In this paper, work focuses on Developing Verification IP (VIP) for AMBA AXI 5.0 protocol achieving successful transactions of read and write according AXI specification. The VIPs are developed using recent methodology called Universal Verification Methodology(UVM). All simulations are done in Cadence Incisive and waveforms are observed and analyzed in Simvision. Incisive Metric Center(IMC) is used for coverage analysis.