Design and Implementation of modified Wallace tree multiplier using Compressors

Abstract

Multiplier is the most required unit in all digital circuits including DSP applications. The demand of high speed processing has been increasing day by day. Hence there is need of high speed multiplier. In this work, Wallace tree multiplier has been chosen. It  is an efficient hardware implementation which multiplies two integers by reducing the number of  partial products. This work  results an  approach for the   reduction of delay in the WTM by using compressors and hybrid adders for partial product reduction. These new adders displays reduction in area and delay compared to the normal full adders. The design is verified and simulated functionally in terms of delay, LUTs and power using Modelsim. Delay and area has been reduced by 60% and 24.36% respectively.

Keywords: Wallace tree multiplier (WTM), Full adder (FA), Half adder (HA), Multiplexer (MUX), Hybrid adder, Compressors.