A Low Power and Area Efficient Design of Dadda Multiplier by exploring 4:2 Compressors and Brent-Kung Adder

Abstract

   In this paper we proposed low power and area efficient multiplier using Dadda algorithm. Here 4:2 compressors are used in Dadda reduction stage and Brent-Kung adders in final stage. The results are compared with the conventional designs i.e. Ripple carry adder, Carry look ahead adders and Kogge-Stone adder in Final addition stage with and without using 4:2 compressors in reduction stage along with full adder and half adder. The proposed multiplier design and conventional designs are simulated on Xilinx Vivado 2019.2. The results shows that the proposed design of Dadda multipliers takes least area and dissipate less power than conventional designs.