A Novel Design CNTFET based Adiabatic Logic Circuit for Low Power Applications

Abstract

As semiconductor industries booming now a day’s results in scaling down the device in the field of VLSI for low power applications. Adiabatic circuit design play a major role in saving of power, the main principle behind this approach is to slow down the operation of the transistor so less amount of power dissipate in the form of heat. The aim of this paper is to reduce the dynamic and static power of circuit by simulating various basic gates like BUFFER, NAND, NOR and XOR based on different types of adiabatic logic circuit with the existing and proposed design to compare the performance parameters in terms of average power consumption and delay with variation in frequencies. For fair comparison of results we have taken same simulation parameters and it is carried out by   HSPICE tool at at 16nm technology with the variation of frequency and temperature ranges. it is observe that proposed circuit saves upto 88% of Average power at 32nm technology & 90% of Average power at 16nm technology.