Design and Analysis of Noise Tolerant, Low Power Wide-OR Domino Logic by using Interconnects in DSM Technologies

Abstract

In Present scenarioDynamic logic approach is used in high performance circuit design because of its fast speed and less transistors count when compared to MOS logic style. The main drawback of the dynamic circuit is the power consumption which is mitigated in domino logic design, another problem lick UNG which is reciprocal to the leakage power and charge sharing problem is also reduces in novel domino circuit design. Here in this manuscript we have introduce RLC interconnects with wide fan-in domino logic there is also leakage reduction technique is incorporated in domino logic design to save the maximum power and increase the speed of the circuit. In proposed design a chain of evaluation network with stacking effect and RLC interconnects in the dynamic node help in reduction of the leakage current and achieve maximum UNG, so overall performance of the circuit improves. With the help of stacking effect and insertion of the current mirror circuits in proposed design achieves more noise immune and improves overall performance parameters when compared with other existing domino logic. Here simulation is performed at 32nm with MOS technology at 100MHz frequency with supply voltage of 0.9V. The proposed domino circuit saves 96.4% power consumption, delay upto 52.4% and UNG 5.6x when compared with other existing circuits.