LOW POWER HIGH SPEED ROBUST SRAM CELLS

Abstract

This paper presents two unique topologies of 11T SRAM cells with. The proposed 11T-A and 11T-B cells effectively reduce power consumption and also decrease delay time of input to be propagated to the output and furthermore improve the Write-capacity by utilizing power-cutoff and compose '0'/'1' just procedures. The 11T-A and 11T-B cells expend low power contrasted with proposed 11T-A SRAM cell. The proposed 11T-A cell likewise shows low power utilization contrasted and existing 11T cell. And 11T-B shows ground cut-off with floating node avoidance assist. Both the proposed cells effectively dispense with coasting hub condition experienced in before power cut-off cells. We additionally present a near investigation of Bias Temperature Instability (BTI) unwavering quality affecting the SRAM execution in a prescient 130nm high-k metal entryway CMOS innovation. 11T-A and 11T-B cells improve postpone all the more effectively. In addition, the proposed 11T-A (11T-B) show less postponement contrasted with proposed 11t SRAM cell. Subsequently, the proposed 11T cells are an astounding decision for dependable SRAM structure at nanoscale in the midst of procedure varieties and transistor maturing impact and can likewise be utilized in bit-interleaving design to accomplish multi-cell upset (MCU) insusceptibility.