Design of Finite field Multiplier for Efficient Data Encryption

  • R. S Ernest Ravindran et al.

Abstract

Galois field (GF) number-crunching circuits find various applications in correspondences, signal handling, and security designing. Formal verification procedures of GF circuits are rare and restricted to circuits with realized piece places of the essential information sources and yields. They likewise require information of the final polynomial P(x), which influences final equipment execution. This paper introduces a PC variable based math method that performs verification and figuring out of GF (2m) multipliers straightforwardly from the entryway level usage. The methodology depends on extricating an exceptional final polynomial in a parallel manner and continues in three stages: 1) decide the bit situation of the yield bits; 2) decide the bit situation of the info bits; and 3) separate the unchangeable polynomial utilized in the structure. We show that this strategy can figure out GF (2m) multipliers in m strings. Analyses performedonsynthesizedMastrovitoandMontgomerymultipliers with various P(x), including NIST-prescribed polynomials, exhibit high efficiency of the proposed strategy.

Published
2019-12-31
How to Cite
et al., R. S. E. R. (2019). Design of Finite field Multiplier for Efficient Data Encryption. International Journal of Advanced Science and Technology, 28(20), 42 - 52. Retrieved from http://sersc.org/journals/index.php/IJAST/article/view/2633
Section
Articles