Design of Modified High Speed Multiplier using Reversible logic and FPGA Implementation in Matrix Multiplication for Image Enhancement

Abstract

In modern VLSI technique, most of the adder design faces problems in four basic constraints namely power, chip area, speed and error occurrence, a modified hybrid VLSI adder 5T transistor design which integrates the logic of both Pseudo-NMOS and XOR Gate is proposed which is used to overcome the issues of accuracy, low speed and power consumption. . This paper proposes a new design for 5-transistor cmos-XOR gate which utilize less silicon area and consumes relatively lesser power than that of the existing 6-transistor and 12-transistor XOR gate designs and more accurate/good at output values when compared with the 4 and 3-transistor logics. The proposed XOR logic is implemented in Ripple carry Adder and its performance is implemented in matrix multiplication for image Enhancement. Image enhancement is one of the most important and fundamental technique in image processing. The main aim of image development is to progress the ocular appearance of an image. Image enrichment is processed out using two Design Methods they are spatial domain and frequency domain. Spatial domain method exactly deals with the image pixels, the pixels values are manipulated to achieve the desired enhancement, while frequency domain technique is based on the manipulation of the orthogonal transform of the image rather than the image itself. Matrix multiplication architecture is used in enhancing the image. An image is converted into pixel matrix which is multiplied by Gaussian filter coefficients. The multiplication is an important fundamental function in an image enhancement and it dominates execution time. In this proposed work the high speed multiplier using modified cmos xor logic and reversible logic gate will be used in matrix multiplication technique. The Modified high speed multiplier performs high speed multiplication operation and consumes less power for its operation. The multiplication will enhance the quality of an image by increasing its resolution. The proposed modified high speed multiplier is designed using backend tool Cadence & VHDL it is implemented through Xilinx ISE 14.5 and System Generator tool is used for the construction of image algorithm in MATLAB.