Design of a Flip-Flop to provide Low latency and to avoid Redundancy for Low Power Applications

Abstract

A flip flop is proposed with few conditions to avoid redundancy for low power applications in cases where the given voltage is almost near threshold level region. This design provides low latency adopting conditional capture to reduce the switching power consumption. This flip operation gives better results compared to other conventional flip flops already exists. Experimental results in a 18-nm CMOS process indicated that the proposed flip flop provided very good lower latency with improved energy-delay product at good percentage of switching activity compared with conventional differential flip-flops