Design Of 8-Bit Low Power Barrel Shifter Using Self Controllable Voltage Level Technique

Abstract

The paper describes how  to design a  low power barrel shifter with less power requirement used in Arithmetic Logic Unit (A.L.U). Now a days  portable systems are required to drive with low power consumption. Barrel shifter plays important role in the arithmetic and logical unit in the Microprocesso , Floating Point Unit (FPU) and also used in the Digital Signal Processing(DSP)for shifting operations. Dynamic  logic circuit design with True Single Phase Clock (TSPC)  suffers from pre charge pulse propagation and Pseudo Dynamic Buffer(PDB)  requires more power. Hence, design of Barrel shifter with Self controllable voltage level(SVL) consumes less power .In this paper  the power requirement of the Barrel Shifter using SVL (TYPE-1,TYPE-2,TYPE-3)circuit  is compared with existing techniques. In this paper results shows that PDB shifter with TYPE-3 SVL circuit dissipates less power compared TYPE-1 and TYPE-2 circuits. The proposed techniques are designed and simulated using Tanner EDA 15.0 Tool for different technologies 250nm, 90nm, 65nm