Implementation of Efficient 2-4 and 4-16 decodersusing Gdi Technique

Abstract

This work main focuses on the design and implementation of efficient decoders due to vast requirement of decoders in security application and communication decrypting it has become essential circuit in todays application this work demonstrates the design of 2-4,4-16 decoders using conventional,gdi,mixe style of design this experiment shows that result of a decoder like 2-4 decoder implemented in all designs and we can see power dissipation decreased using gdi by 57% and delay by 72% than using of previous designs and complexity , area of decoder circuit is  reduced .