Multiplexer based High Speed Double Precision Floating Point Multiplication

Abstract

In this paper, double precision floating point multiplication is designed and analyzed using two algorithms such as karatsuba algorithm and vedic algorithm. Different modified 2x1 multiplexer techniques are incorporated in both Karatsuba and vedic algorithms to improve the speed. Further, the comparative analysis is made for both algorithms in terms of speed and area. From the results, it is inferred that double precision floating point multiplication with karatsuba algorithm using modified 2x1 multiplexer model V offers improved performance with high speed along with improvised in area utilization. than that of existing techniques. All the blocks involved for floating point multiplication are coded with Verilog and synthesized using Xilinx Vivado Tool.