An Efficient CMOS Current Reuse Capacitive Divider LNA Circuit for Better Communication

  • Mukku.Pavan Kumar, S. Vasu, N. Pavan Kumar, P.C Rupesh, T. Suraj Kumar

Abstract

            This paper presents the design of low voltage, less power consumption efficient CMOS cascode LNA with moderate gain and bandwidth with a minimum chip area. In communication system, receiver is the major part. The communication system will be weaker, if the receiver gets weak signals from the antenna. As wireless transceivers growth increases in high-performance RF and microwave circuits which have been integrated into single IC. The receiving portion is efficient for amplification due to improved parameters including gain, bandwidth, linearity and chip area and low noise amplifier (LNA). This will result in a strong amplification along with less noise and low power consumption receiver section in the communication part.

            We design CMOS based current reuse capacitive divider LNA with input inductance for best input impedance matching. The Pre-and post-simulation along with synthesis in terms of NF, gain, and average power consumed shows the circuit is an efficient design.

Published
2020-06-06
How to Cite
Mukku.Pavan Kumar, S. Vasu, N. Pavan Kumar, P.C Rupesh, T. Suraj Kumar. (2020). An Efficient CMOS Current Reuse Capacitive Divider LNA Circuit for Better Communication. International Journal of Advanced Science and Technology, 29(04), 4832 - 4840. Retrieved from http://sersc.org/journals/index.php/IJAST/article/view/24910