Binary Multiplier (n-Bit Size) Design, Implementation, Analysis and Comparison of Various Logics

Abstract

The Multiplier is the most important component in an ALU (Arithmetic and Logic Unit). The multiplier of various bit-sizes can be designed and implemented using various logics like standard, Vedic, tree-structure and so on. Each and every other logic has its own importance; For example, standard logic is the most common logic and well-known logic, used worldwide to perform multiplication. While, Vedic logic is the faster logic, in terms of operation compared to the standard; although consumes equal area as in standard logic. Whereas, the tree-structure logic involves serial-parallel processing combination and hence it is the fastest logic in terms of operation compared to Vedic logic, but consumes more area on comparison with the standard and Vedic logic.  As the VLSI design involves trade-off; depending on various specifications, one can choose the specific logic. The Implementation is done using MS-Excel sheets, Logisim (open source), Xilinx & Cadence EDA tools.