Implementation of Vedic Multiplier for Digital Signal Processing Application

Abstract

Speed is the peak area of interest in new   technology. Multiplication is one of the important functions in all mathematical operations multiplier is basic building block in digital signal processors. multipliers need to be modified to increase the speed of execution.  In ancient Vedic mathematics there are several methods for multiplication operation. As compared to array and tree multipliers Vedic multiplier are used due to their high speed of operation and low power consumption. There are sixteen sutras in Vedic multiplication. For higher bit of multiplication Urdhva Tiryakbhyam sutra is used. Using Urdhva Tiryakbhyam sutra large number of high-speed Vedic multipliers have been designed. In this paper ,16 X 16 Vedic multiplier will be designed for digital signal processing application using VHDL. Out of the sixteen sutras of Vedic multipliers, one of the sutras will be used to design multiplier. The focus of this work is achieved high speed and low power. The result will be then compared with similar kind of work