Implementation of Area, Power Efficient, Less Complex Filter Bank for Channelization of Software Defined Radio.

Abstract

 In software defined radio it is important that it has ability to extract numerous channels of different communication standards .Software defined radio use digital filter bank for channelization of input signal consisting of multiple radio channels. The complexity  ,area, power are important issues in channeliser design. In this paper we propose a coefficient decimation based filter bank for uniform channelization scenario using FIR filter as a modal filter  .In the proposed filter bank low pass ,high pass ,band pass  responses are obtained by coefficient decimation .These frequency responses are mathematically operated upon using addition ,subtraction and cascading operations. The modal filter is designed using Baugh Wooley multiplier and Ternary adder. This architecture is implemented in Xilinx XC5vlx330-1ff 1760 field programmable gate array. This combination has resulted in less area and power of filter bank. The comparison with DFTFB filter bank shows 72 % reduction in area, with the CDFB filter bank shows 21 % reduction in area. The area complexity reduction is because of reduction in adder elements using ternary adder. The comparison of power shows 62 % , 30 %  reduction in power as compared to DFTFB, CDFB . The multiplication complexity of proposed method is improved by 44 % as compared to DFTFB, 12 % as compared to CDFB.