Hardware Efficient Hybrid Wireless Crypto Processor Using Enhanced Advance And Side-Channel Resistant Authenticated Encryption Standard
In this modern era, communication or data transmission plays an important role in a human’s life and carried out in wireless medium. Cryptography techniques are necessary for confidential data transmission in wireless media, which protects electronic data in communication network. Many algorithms that are cryptographically secure are not easily implemented in computer applications especially in hardware. In this paper, we propose a hardware efficient hybrid wireless crypto processor (HWCP), which combines two block ciphers such as enhanced advanced encryption standard (AES) and side-channel resistant authenticated encryption with masking (SCREAM). Generally, the hardware cost of hybrid processors are very high, here we use composite field arithmetic (CFA), on the fly key expansion, and order change to reduce the hardware parts in the encryption algorithms. The main objective of this design is to propose hybrid crypto processor, which is complex and not easy to crack the keys from malicious. The proposed HWCP design maximizes the security via increasing the complexity of cracking keys. Moreover, the proposed HWCP design is implemented with parallel sub-pipeline manner that increases the throughput. The proposed HWCP design synthesized with different FPGA families are Virtex-6 (xc6vlx75t-2), Artix-7 (xc7a100t-2), Kintex-7 (xc7k70t-2) and Virtex-7 (7vx330t-2) in Xilinx tool. The performance comparison of proposed HWCP design is compared with existing designs in terms of hardware utilization, power consumption and maximum operating frequency.