A Scalable Energy-Efficient Approximate 16bit Multiplier for Image Processing Applications

Abstract

Approximate circuits has been considered for applications which can endure certain loss of precision, but with improved execution and vitality effectiveness. Multipliers are essential math circuits in numerous applications, for example, advanced signal handling (DSP) with major emphasis in Digital Image Processing. In this work, a improved approximate multiplier which has lower power utilization and a short critical path is used. The customary multipliers is proposed for superior DSP applications, especially digital image processing application. This multiplier uses a structured approximate adder, which limit the carry propagation for a faster, a shifter and a load module to perform the desired multiplication operation. Further a Discrete Wavelet Transform is considered as an application where the designed multiplier is integrated. DWT architecture comprise of Line Buffers, Lifting Block, and PIPO. RTL Verilog is used for coding the architecture and is synthesized using Xilinx ISE and Vivado tools, targeted on xc7z010-3clg400 device of FPGA. The delay obtained was 6.540ns and the total signal power dissipation for data path is 0.00591w. To validate the DWT image processing application MATLAB scripting is used to view and evaluate the processed data sample from the Verilog code.