Design and Implementation of Fault Tolerant Hybrid Full Adder Using Inverter

Abstract

Fault tolerance is a property that enables a system to continue operating properly in the event of one or more faults within of its component. The fault further classified into transient fault and permanent fault. Overall System performance can be effect by the presence of fault. The aim of this paper is to design a fault tolerant hybrid full adder so that the system will satisfy the requirements despite failures. We designed to detect and repair any faults in a circuit using self checking and self repairing full adder. It can also identify the location of faults. The conventional full adder involves many numbers of components. And also area and power will be high. So we introducing hybrid full adder with less number of logic gates. And also we implemented a multiplier using this proposed system. The proposed design is simulated by Xilinx and synthesized by ModelSim. This system can solve the major problem occurring in real-time application.