Design of Mux-Dual Latch Circuit for Inter-Chip Communication

Abstract

In high speed transceivers, Serializer is the fundamental device for converting parallel data into serial data. In traditional methods, we employ the MCML based multiplexer circuit in Mux block of Serializer device which has different restrictions like small output voltage swing, more power dissipation and the noise tolerance. To overcome these problems, a delay combined current mode Multiplexer incorporating PMOS based dual cross coupled latch circuit was used to replace the traditional circuit in Mux block of Serializer device in this project to manage noise tolerance, power consumption problems and to maintain stable rail-to-rail output voltage swing and signal standard at differential output. The results of newly introduced Mux block circuit of Serializer device was executed in 90-nm CMOS Cadence Virtuoso platform. The new Serializer design is proved to be more noise free circuit with high output voltage swing along with the higher data rate of transmission.