Pre amplifier Latch CMOS comparator using 130nm Technology for Analog to Digital Converters
In this papera Pre amplifier latch CMOS comparator using 130nm technology is analyzed. In this clock driven preamplifier latch circuit is being used. The main purpose of this project is to reduce the power dissipation of comparator and it is used in analog to digital converter (ADC) to increase their speed . This comparator will be designed by using 130nm CMOS technology. From earlier work it is observed that circuit reduces the amount of kickback noise and offset voltage. It is implemented by using the Mentor Graphics software. Mentor Graphics software is a technology leader in Electronic Design Automation (EDA), providing both the software and hardware solutions that enable companies to develop better electronic products faster and more cost effectively.