Area Optimized Fir Filter Design Using Baugh-Wooley Multipier and Carry Look Ahead Adder

Abstract

In present day’s digital communications, Finite Impulse Response (FIR) filter plays vital role in major application of Digital Signal Processing (DSP), Speech processing based VLSI applications. Basic architecture of FIR filter consists of adders, multipliers and ROM to perform addition and multiplication for accumulation that consumes significant area. In previous research, Baugh Wooley Multiplier (BWM) and Carry Look-ahead Adder are used in Processing Element (PE) multiplication and accumulation to achieve efficient design. This architecture reduces resource area only in processing elements. However, Look Up Table(LUT) that stores coefficients utilize more LUT/Slices due to its sequential circuit nature. This paper considers the optimization of hardware resources without sacrificing the frequency response and without degrading output signal precision. An area optimized LUT based filter design is proposed to reduce filter area by using shift and complement algorithm. This proposed method reduced ROM size by 40% of total area from previous research.