Reconfigured SDR for Wireless Communication with Reduced Power Consumption and High Throughput
This paper proposes a comprehensive analysis and implementation of FPGA architecture for low routing power and clock gated CLBs. As the FPGA has thousands of logic blocks and hard embedded micros spread across the chip, more numbers of routing lines and switch boxes are required. Also the clock network is built with same routing resources. The Configurable logic blocks with clock gating will allow reducing the dynamic power. The logical equivalence of CLB inputs will help to reduce the routing congestion and also to improve the timing of the design. The logic operations are in conventional carry select adder (CSLA) and binary to excess 1 converter (BEC) based CSLA to study the data dependency and to identify superfluous logic operations. The new logic formulations have been proposed by eliminating all the redundant logic operations present in the conventional CSLA. In the proposed scheme, the carry-select operation is scheduled before calculation of the final-sum. The proposed CSLA design requires significantly less area and delay than the proposed BEC-based CSLA. Due to small carry-output delay, the proposed CSLA design is good for square root (SQRT) CSLA. As per the theoretical figuring, the proposed SQRT CSLA involves nearly 35% less area lag product than the BEC based SQRT CSLA, which is the best amongst the current SQRT CSLA designs. FPGA synthesis result shows that, the BEC-based SQRT CSLA design invokes large Area-Delay Product and consumes more energy than the proposed SQRT CLSA on average for different bit widths.