Area-Delay Efficient Fixed Stage Carry Skip Adder

  • Athappan.M, Dr KR.Santha

Abstract

 A carry skip adder (CSA) has a several advantages such as improved delay and high precision when compared with other adders. Several stages of CSA’s are linked each other to design a group of CSA, which reduces the overall critical path delay. The fixed stage CSA (F-CSA) and the variable stage CSA (V-CSA) provides better performance in terms of power and delay. In the proposed adder, area is reduced by using modified XOR gate and the results were compared. Basic definition of the adder contains fixed stage size. Proposed F-CSA reduces critical path delay of the adder while compared to the V-CSA. Area is reduced by using proposed F-CSA and modified XOR gate. The proposed 16-bit F-CSA and V-CSA was simulated using Xilinx and Cadence RTL encounter using 90nm technology and the results were compared. The ADP and PDP of the proposed fixed stage adder were reduced by 5.3% and 5.46% respectively. The MAC with proposed F-CSA are coded in Verilog HDL and simulated in Xilinx ISE 9.2i for 32-bit. Area Delay Product and Power Delay report of both proposed adders and MAC were obtained from Cadence RTL encounter using 90nm technology. The ADP and PDP of the MAC using proposed F- CSA were reduced by 39.9% and 8.34% respectively.

Published
2020-05-15
How to Cite
Athappan.M, Dr KR.Santha. (2020). Area-Delay Efficient Fixed Stage Carry Skip Adder. International Journal of Advanced Science and Technology, 29(7), 3609-3617. Retrieved from http://sersc.org/journals/index.php/IJAST/article/view/23047
Section
Articles