Low Complexity FPGA Implementation Of FFT Computation For OMP CS System Using Fused Arithmetic Technique

Abstract

The floating point computation has been used extensively in many techniques to mitigate the problems over erroneous fixed point analysis. Identification of an appropriate technique to reduce the design complexity of floating point play key role since hardware hungry floating point units are not suitable for complex arithmetic like FFT (Fast Fourier Transform) computation. This Proposed work concentrate on the Deduction of redundant calculation in both Floating Point and FFT Building Block unit establish on hardware fusion technique. The scattered Arithmetic (SA) based on CSD [Canonical Signed Digit method] can be useful for mantissa calculation. This proposed paper Research analysis also propose radix 2, radix 4 and radix 8 Fast Fourier Transform Calculation algorithms with development in functioning by fused floating point mathematics calculation units. High speed Multiplication function Calculation algorithm is used to control the operating time and fixed hardware circuit block to implement the Fast Fourier Transform. Additionally, higher order radix indices are enhanced and implemented without adding any pipelining and parallel operating techniques. The effect of quantization loss due to the fixed point arithmetic errors and its impact on overall OMP (Orthogonal Matching Pursuit) system performance is analyzed and compared with précised floating arithmetic through simulation. The comparison outcome shows that the proposed Algorithm will reduce the area, operating frequency and produces high Efficiency in throughput. The results show that the multiplier less mantissa computation model exhibits area efficiency in the range 5%-15% over various radix indices with maximum of 24% energy efficiency.