ERROR ANALYSIS FOR DWPTHARDWARE REALIZATIONUSING APPROXIMATION

  • G.Renuka et al.

Abstract

An error analysis for Discrete wavelet packet transform (DWPT) architecture using approximation computational methodology is presented in this paper. The multiplier adder unit of DWPT is replaced by Shifter–Adder -unit to decrease the complexity of parallel structures. Shift add register (SAR)approximate arithmetic architecture designs are proposed for low complexity multiplier –less design that can be an substitute for existing multiplier based designs for realization of multilevel DWPT.

Published
2019-12-21
How to Cite
et al., G. (2019). ERROR ANALYSIS FOR DWPTHARDWARE REALIZATIONUSING APPROXIMATION. International Journal of Advanced Science and Technology, 28(17), 465 - 478. Retrieved from http://sersc.org/journals/index.php/IJAST/article/view/2295