FPGA Implementation of Reconfigurable FIR Filter using Vedic Design with CLA Adder

Abstract

Nowadays, Reconfigurable Finite Impulse Response (RFIR) filter is required for most of the Digital Signal Processing (DSP) applications. In that, the reconfigurable filter frequently changes the coefficients while performing the operation. In this paper, Vedic Design with Carry Look Ahead adder is used to design the RFIR filter (RFIR-VD-CLA). This RFIR architecture is designed using different bits and taps such as 4 bit & 3 Tap, 4 bit & 7 Tap, 8 bit & 3 Tap, and 8 bit & 7 Tap. For all the architectures, the FPGA and ASIC performances are evaluated. Cadence 180nm and 45nm technology have been used for calculating area, power, and delay of the entire architecture. From Xilinx, FPGA performances such as LUT, flip flop, slices, and frequency have been evaluated. RFIR-VD-CLA architecture utilized 103716 um2 area, 693908 nW power, and 130ps delay in 180nm technology. RFIR-VD-CLA architecture has better ASIC and FPGA performances than existing architectures.