DFT Flow for Automotive SOC

Abstract

NXP DFT Tool allows to build a chip-level design with a flexible architecture. NXP DFT Tool performs various consistency checks on the input files which prevent from specifying defective input. The main input for NXP DFT Tool is four tables with the description of the pads, the top-level multiplexers (tmux), the IEEE 1149.1 instructions and the user registers. The main output of the NXP DFT Tool are RTL (Register-Transfer Level), design data files, BSDL (Boundary-Scan\ Description Language) files and control files. NXP DFT Tool is proprietary of NXP. Experimental results show that for an Automotive System on Chip (SoC) design, the compression obtained per pattern is 3.03X with maximum scan chain length of 325 using 4 external scan channels. It is further optimized to achieve compression obtained per pattern of 4.68X with maximum scan chain length of 125 using 5 external scan channels.

Keywords–NXP DFT Tool, RTL, BSDL, tmux, design data files, control files, ATPG, Tessent