Performance Estimation of the Combinational Circuits Using Carbon Nano Tube Field Effect Transistor
Carbon Nanotube Field Effect Transistor-based (CNTFET-based) logic gates and multiplexer design is proposed with improved Power Delay Product (PDP) in different threshold voltage levels. In this paper, CNTFET NAND, NOR, Inverter and multiplexer is designed and simulated in HSPICE tool and their performances are compared with existing MOSFET design. Using HSPICE simulation, CNTFET based multiplexer have reduced power consumption and power delay product respectively 85% and 53% than the CMOS design. This shows CNTFET-based design has tremendous amount of performance improvement. In this paper, impact of Stanford 32nM CNTFET library is used to design the combinational circuits.
Keywords: Nano meter technology, MOSFET, CNTFET, power delay product.