Implementation of 16-Bit LFSR Logic Gates for Low Power Applications In BIST

Abstract

In the current front-line innovative development in VLSI hardware for upgraded power applications, the proposed research work predominantly envisions in executing linear feedback shift register (LFSR) of high-power efficiency, to deliver high stochastic patterns for low power systems under Built in Self-test (BIST). Execution of Reversible D Flip Flop, Feynman Gates and Double Feynman Gates utilizes SNG gate and Fredkin of 16-bit LFSR. The projected process limits area and power utilization when novel structuring fashion of reversible LFSR are used with respect to traditional configurations.  The present structure is utilized to applicate BIST under low power systems by utilizing Fredkin and SN gate which is further derived to implement logic gates AND, XOR, XNOR and NOT by utilizing SNG design.  These results when looked over delivers superior area usage timing with respect to traditional strategy.