2-bit Vedic Multiplier Design Using Urdhva-Tiryagbhyam and Modified-Gate Diffusion Input Technique

Abstract

         This paper presents a Vedic Multiplier design which are designed by adopting Modified Vedic Mathematics sutra called Urdhva-Tiryagbhyam. The proposed Vedic multiplier scales down the number of steps required to obtain the final product, thereby reducing the delay of the circuit. A high-speed multiplier depends mainly on adder block performance. Improving adder block performance, the total energy consumption is reduced by 28% and delay factors of the augmented multiplier module are the main focal points of this paper. Thus the speed of the multiplication is increased by 30%. The proposed 2-bit Vedic Multiplier circuit design using Modified-Gate Diffusion Input (GDI) Technique is used as a primary element in configuring the structure of higher order Vedic multiplier circuits. Modified-GDI Technique overcomes all the drawbacks of original GDI cell such voltage swing reduction caused due to threshold drops which leads to increase in static power dissipation and performance reduction. This design of 2-bit Vedic Multiplier is done using Mentor Graphics in the CMOS 130 nm technology.