An Optimized VLSI Based High Performance Architecture for Lossless Data Compression
Data compression is method of encoding rules, which allows substantial reduction in total number of bits to transmit or store file. To archive or transmit binary files or text, lossless data compression is utilized, which is need to keep data intact at any time. LZRW1 (Lempel Ziv Ross Williams) and LZW (Lempel Ziv Welch) was mainly used for lossless data Compression. But LZW takes more time to Compress and decompress data. LZRW refers to variants of LZ77 lossless data compression techniques with emphasis on increasing compression speed by use of hash tables and other methods. In order to provide high throughput of data, a hash table is implemented by replacing the dictionary in LZW. This method has worst case running time. It adapts quickly and neglects initialisation in making it fast as well as powerful for small blocks of data and large ones. The speed of compression has been increased by four times that of LZW.The compression ratio obtained also be relatively same as that of LZW.The proposed algorithm was implemented in system verilog, simulated by using Questa sim tool and synthesised in Xilinx Vivado.