Design of FIR Filter Using High Speed Carry Select Adder for SDR

Abstract

For Software Defined Radio (SDR) and future signal processing applications the efficiency of the system majorly depends on the performance of Digital Signal Processor (DSP). One of the major task in the processor is Multiply And Accumulation (MAC) unit. The adders are the main components in MAC unit. In this work an efficient high speed Carry SeLect Adder (CSLA) is proposed for the design of Finite Impulse Response (FIR) filter. In the existing method the adder part has high delay which causes less speed when compared with the proposed method. Without degrading the function of the FIR filter the proposed 32-bit buffer based CSLA has offered the reduction in delay. The proposed CSLA offers 14% reduction in delay and slight increase in number of slices and LUTs. The proposed 4-tap FIR filter offers the 3% reduction in delay when compared existing filter designed with conventional CSLA using BEC and the validation is done by Modelsim 6.3c tool and synthesized using Xilinx 12.4 ISE.