Application of Testability Analysis in Hardware Security
In recent years, VLSI testing has been gaining abundant prominence in hardware security paradigm. Testing not only ascertains correctness of circuit designs but also provides feedback to designers to improve existing designs. Hardware attacks at gate level of abstraction largely target circuit nodes with poor testability metrics. Identification of regions of a logic circuit which are poorly testable is referred to as Testability Analysis. In this paper we explore the possibilities of extending testability analysis for the detection of Hardware Trojans (HT). The effect of HT insertion on the system testability metrics is evaluated for c-17 benchmark circuit and the results are presented. This research also introduces a software tool developed to automatically generate the testability parameters namely the controllability and observability of each node in the circuit using MATLAB. The developed testability analysis software tool accepts Hardware Description Language (HDL) file as input and generates the controllability and observability values of each node described by the HDL. These testability parameters can further be utilized to identification and hence classification of unsecure nodes.