The Tiled Cache Implementation for High Performance Processor

Abstract

Embedded Processors demand cache hierarchies which can satisfy needs of industries, improvisation in performance and reduction in power requirement. Here, work involves introducing tiled cache implementation for high performance processor. Tiled Cache memory implementation involves basic operation Search, Transport and Replacement. From VLSI implementation  tiles incur minimal latency and area. Tile cache implementation involves search, transport and replacement operations. Tile cache improve the performance in multi core processor. We use Xilinx simulation tool to model tile architecture for cache.