Design of scan chain using level sensitive flip-flops for VLSI Testing

Abstract

In CMOS digital system design, the power and area requirement are the two major challenging issues.
Therefore, by considering these two issues proposed a scan chain designing strategy by replacing all
edge-triggered flip-flops into level-triggered flip-flops to reduce power and area requirement. In
today’s DFT(design for testability) based VLSI testing, structured scan design takes important role.
Compared to Ad-hoc DFT based testing, using scan based design it is possible to observe and control
the internal states/nodes of CUT(circuit under test) easily compared to Ad-Hoc DFT based testing. The
internal structure of the flip-flops shows that area utilized by the level triggered flip-flops is less
compared to the edge triggered flip-flops. The timing problem in level sensitive flip-flops is overcome
by using external non-overlapping pulsed clock signals. The design is power, area efficient and
experimental results are presented for ISCAS 89 benchmarks. Using the proposed method it is achieved
satisfactory reduction in power and area requirement.