Performance Analysis of Double-precision Floating-point Adder using Prefix Tree Adders

Abstract

Digital circuits such as microprocessors and digital signal processors make use of a key component
known as binary adder. The speed of the ALU depends greatly on these adders. This proposed work deals
with verifying the functionality of a number of fast adders using Verilog HDL. A performance analysis
was done on various 52 – bit Prefix Tree Adders on the basis of propagation delay and number of LUTs
on Virtex – 6 FPGA of speed grade -3 using Xilinx 14.7 ISE simulation tool. Based on the analyses,
Knowles (842111) Prefix Tree Adder has been used for implementing a double precision floating-point
adder since it has proved to be the fastest among the adders. The described double precision floatingpoint adder which uses a 52 - bit Knowles (842111) Prefix Tree Adder for mantissa addition was found to
have a 43.24% reduction in delay as compared to the 52 – bit Brent-Kung Prefix Tree Adder at the cost of
9.18% increase in the number of slices (LUTs). All the exceptions pertaining to floating-point operations
are taken into consideration in the design. However, a compromise between propagation delay, number
of LUTs and power is always there.