Design of FinFET based Resistive Keeper Circuit for NORA logic based Serial Adder and 4x32 Memory Array

Abstract

With the advancement in technology, Fin Field Effect Transistors (FinFETs) replaced Metal Oxide
Semiconductor Field Effect Transistors (MOSFETs) in to satisfy the needs. Dynamic logic family circuits
being faster than conventional Complementary Metal Oxide Semiconductor (CMOS) circuits, have been
considered for the analysis. To overcome the disadvantage of larger dynamic power dissipation in No
RAce (NORA) logic based dynamic circuits, a keeper has been designed. Considering the aforementioned
factors, the objective of this project is to design a keeper for NORA logic based dynamic circuits. A
serial adder is a practically relevant circuit in many preliminary filter designs; therefore it is deemed
useful to improve its power efficiency by implementing the keeper architecture. D-latch, D-flip flop, shift
register, full adder and serial adder are methodically built and analyzed with respect to power
consumption using Cadence-Spectre. Memory being the most used component of any system should have
less dynamic power dissipation. The storage cells in the memory can be implemented using the dynamic
logic with the keeper cells. A comparison between the memory cells with respect to dynamic power
dissipation is done by implementing them using Dynamic D-flipflops, NORA logic D-flipflops and NORA
logic with resistive keeper cells.