Performance Analysis And Design Of 6t Sram Cell Using Different Circuit Techniques

Abstract

Power Dissipation Is An Important Constraint In Today’s Vlsi Technology. In Earlier Days Dynamic
Power Dissipation Is Regarded As Major Source Of Power Dissipation. However, Because Of
Technology Scaling The Static Power Predominates The Dynamic Power. Static Power Is Mainly
Depending On Leakage Current That Flows When The Circuit Is In Idle State. This Leakage Current
Increases Exponentially With Reduction In The Supply Voltage And Threshold Voltage [1][2]. Therefore,
It Is Necessary To Control The Leakage Power By Early Estimation. The Memory Unit In Today’s
Digital Systems Are Built Using Dram Or Sram Cell. Sram’s Are Widely Used In The Form Of Register
Files, Buffers, Instruction Windows And Caches In The High-Performance Processors. Sram Also
Contribute Some Amount Of Static Power. Through This Paper We Are Comparing The Performance
Analysis Of 6t Sram Cell Using Different Circuit Techniques In Terms Of Power Dissipation And Delay.
All Different Circuit Designs Of Sram Cell Is Simulated Using Hspice In 90nm Process Technology With
Bsim4 Mos Transistor Models Of Level 54