A Low Power FPGA Implementation of SHA3 Design

Abstract

In the recent decades, quite a lot of real time data has been digitalized, thereby making communication primarily happen through phones or internet as a result of which several difficulties like maintaining confidentiality and authentication of data are becoming the need of the hour. Open networks however serve as a gateway for communication to happen effectively. Thus, due emphasis has to be laid on the development of various tools and techniques in orderto defend ourselves from the adverse effects of the same. In this process of securingvital information from the posed threats, a cryptographic hash function comes as a rescue and helps in accomplishing our objectives of security.
SHA3 is acompetent hashing technique which has been executed successfully in FPGA and has replaced several other hash functions like SHA – 1 and SHA - 2. The earlier algorithms despite having similar structural designs internally were subjected to various hash attacks. Thanks to the Quartus tool, the suggested SHA3 algorithm has been implemented with various nanometre technologies like 65 nm and 90 nm in cyclone II and cyclone III. This paper throws a detailed analysis on three important parameters such as area, power and delay. Furthermore, about 47% of low power during data transmission has been achieved through the suggested algorithm.