Design and analysis of an ultra low power energy efficient hybrid 1- bit full adder

Abstract

In the era of digital human machine interaction, the success rate of any electronic device is dependent
on a design parameter of circuit such as the architectural layout, power dissipation and delay. The
key role of such electronic device is to provide the lower power consumption and long battery life that
can perform the arithmetic logic operation such as addition. Therefore, in this paper we proposed the
hybrid low power, energy efficient one bit full adder circuit. The simulation of the circuit is performed
using Mentor Graphics Pyxis EDA tool in 130 nm technology at 27 ◦C. Performance metric of such
power dissipation, propagation delay and PDP are evaluated. Further, the comparative performance
of the circuit is also presented with the previously proposed work. Finally, the proposed one bit full
adder gives better power dissipation with respect to other full adder circuits.