Design of Dynamic Latched Comparator for High Speed ADC Applications

Abstract

Low power, the high-speed comparator is the essential unit for each ADCs circuit. In this paper, a
charge sharing technique which is used to reset the fully differential double tail dynamic comparator
is presented. This technique is used to reduce the delay for both reset and preamplification phases by
sharing the charge between both of the output nodes. Instead of fully charging the output nodes to
VDD, they are charged to half of the power supply. Due to this, overall power consumption for this
circuit is also decreased. The proposed design takes less time for comparison and reduces the overall
delay. This circuit is designed and simulated in 0.18µm feature size on Cadence Virtuoso. The
simulation result shows, the delay is 122.8ps and it consumes only 105.72 µW power