Design and Implementation of Area Efficient Vedic Multiplier for High Speed Applications

  • Tripti Sharma

Abstract

Multiplication which is a common arithmetic operation is of a great use in the technological
applications. It is used in typical digital signal processing applications, image processing, FIR
structure build up. These processes use multiplier as one of their main hardware component and the
speed of entire system depends on the multiplier. This paper, have a novel architecture of the Vedic
Multiplier. Vedic multiplier is based on the ‘Urdhava-tiryakbhyam’ method. The multiplication it
holds is of two 16 bit numbers. The architecture is made up of the adders such as half and full-adder,
compressors, Carry select adder. The design is coded using Verilog language and synthesized with
Xilinx ISE 13.1 Using Spartan 3E series of the FPGA. The combinational delay for the proposed
16×16 Vedic multiplier is 32.352 ns and the number of IOBs used is 40%. The results are also
compared with the other multiplier architectures. The results show the better speed performance and
less area usage.

Published
2020-05-20
How to Cite
Tripti Sharma. (2020). Design and Implementation of Area Efficient Vedic Multiplier for High Speed Applications. International Journal of Advanced Science and Technology, 29(10s), 1620 - 1626. Retrieved from http://sersc.org/journals/index.php/IJAST/article/view/16536
Section
Articles