FPGA Implementation of Low Complexity and Area Efficient Fast Bilateral Filter for Image Denoising Applications

Abstract

Bilateral filter (BF) is a type of edge-preserving smoother, which is widely utilized in most of the image processing, computational photography and computer vision applications. Earlier, there have been several proposals for the field-programmable gate array (FPGA) implementation of BF which utilizes pipelining and to obtain the higher throughput. This article proposed FPGA implementation of low complexity and area efficient fast BF which utilizes modified recursive box filter (RBF) with the usage of modified carry select adder (MCSA) to speed up the execution time and diminish the occupying area instead of ripple carry adder (RCA) employed in conventional RBF. In addition, image denoising application also examined with proposed fast BF. Extensive simulation and hardware results discloses that the proposed FPGA implementation performed superior to the conventional filtering techniques. Furthermore, quality assessment of denoised image in terms of evaluation metrics such as peak signal to noise ratio (PSNR) and structural similarity (SSIM) index also provided.