A Functional Model for Hardware Security in Logic Circuits

  • MusalaVenkateswaraRao ,Yenumala Dileep,Punnamaraju Likhita,Tummala Purnachand

Abstract

Several hardware protection studies seek to thwart hacking, overbuilding, and reverse engineering (RE) by obfuscation of IC. This briefly elaborates the  hardware defines mechanisms to resolve the vulnerabilities and suggests a realistic system of logic obfuscation with small overheads to deter a RE adversary from gate-level. Experimental tests show the low field, power and zero overhead efficiency of the proposed shredding technique. We address the approach by incorporating hardware design obfuscation schemes to protect the present design against various forms of attacks. Hardware obfuscation is also a technique which modifies an integrated circuit to deliberately mask its functionality and schematics. It was suggested as a hardware protection mechanism against reverse engineering, theft of intellectual property (IP), and overbuilding of integrated circuits (IC). IP vendors obfuscate their concepts in the product flow using a series of keys and supply the product house with these keys.

Published
2020-05-13
How to Cite
MusalaVenkateswaraRao ,Yenumala Dileep,Punnamaraju Likhita,Tummala Purnachand. (2020). A Functional Model for Hardware Security in Logic Circuits. International Journal of Advanced Science and Technology, 29(7), 1217 - 1222. Retrieved from http://sersc.org/journals/index.php/IJAST/article/view/15109
Section
Articles