Verification of Real Boot Code at System on Chip (SOC) Level Using GLS

Abstract

Now-a-days System on Chips (SoC) are the major and critical key products in the world of electronics industry. According to Gordon Earle Moore number of transistors in a dense integrated circuit doubles about every two years resulting in smaller sized technology day by day. So, probability of any SOC/IP failure is more often in production and we can’t predict that the final chip will work as expected.So,lot of verification is needed before trust can be secured. Verification of SOC/ASIC starts as soon as architecture/microarchitecture is defined in any industry. This a cyclic process to ensure the functional correctness of the specific design specification before tape-out. In order to increase our confidentiality on any chip and to increase its lifetime we are introducing Gate Level Simulations (GLS). With the increase in design sizes, the complexity of gate level simulations at 14nm technology nodes and below is responsible for longer run times, high memory requirements. As a result, in order to complete the verification requirements on time, it becomes extremely important for GLS to be started as early in the design cycle as possible, and for the simulator to be run in high-performance mode.In this paper we mainly focus on verifying real boot (reset test) logic working for entire SOC properly or not using Gate level simulation.