Low Power CMOS Ring Oscillator with an Enhanced Frequency of Operation
This paper presents a new Complementary Metal Oxide Semiconductor (CMOS) single ended ring oscillator to enhance the frequency of oscillations while consuming less power. The proposed ring oscillator is designed based on a mechanism called sharing that minimizes the transistor count. The proposed 11-stage ring oscillator designed in 90-nm technology results in 14.06 % and 6.05 % improvement in power dissipation while attaining 16.4 % and 145.9 % enhancement in the frequency of oscillations compared with the ring oscillators designed using two existing delay cells. Jitter caused due to supply noise is analyzed. Supply noise jitter in the proposed ring oscillator is comparable at lower frequencies of the noise signal and performs better at higher frequencies. We have designed ring oscillators of various stages ranging from 5 to 15. Comparison of the proposed ring oscillator with the oscillators designed using three existing delay cells is made in terms of power dissipation and frequency.
Keywords: CMOS ring oscillator; low power dissipation; oscillating frequency; jitter; supply noise.